U.S. Pat. No. 4,228,528 describes a semiconductor memory chip that includes spare rows and columns of memory cells, spare decoders, and other various spare circuitry. Each spare row has a separate decoder. One problem is that the pitch (width) of a spare row decoder is substantially greater than the pitch (width) of a spare row, and accordingly the area of the silicon chip increases and yield correspondingly decreases.
It is desirable in folded bit line type semiconductor memories to use spare rows but to reduce the number of spare decoders per spare row from the 1:1 ratio of the above-described memory.